Like AMD's Hypertransport technology, PCI Express is a 2-way, serial connection that carries data in packets, similar to the way it is transferred over Ethernet connections.

The PCI Express bus is no longer a single parallel data bus through which all data is routed at a set rate. Rather, an assembly of serial, point-to-point wired, individually clocked ‘lanes’ each consisting of two pairs of data lines carries data upstream and downstream. As the technology goes to market, each of these lanes is capable of a 2.5Gb/s data rate in each direction. The overall sustained transfer rate roughly equals 250MB/s.

PCI Express was designed with future upgrades in mind, and should see increased results with later enhancements. Where the real performance benefit comes in is when more than one lane is added to a given point-to-point route. Lanes can be stacked together to increase the amount of bandwidth available to specific areas of the I/O system, such as the video card slot, for example.

This technology has a couple of immediate benefits. First of all, the amount of trace routes on any given motherboard areconsiderably reduced by the adoption of point-to-point circuitry.

Using 4 routes instead of 32 for a basic connection, you can see how motherboard manufacturers might well be enthusiastic about this technology, as this would significantly cut the costs of producing motherboards in the long term. Secondly, since each lane is exclusively used for communication between two points, there is no sharing of the available bandwidth.

The objective then, was to create an I/O bus technology that will have the staying power that 32-bit PCI slots have enjoyed, a decade or more into the future. It seems like it has been a success thus far.