SiS to Create Competitive Advantage of DRAM with
Pioneering CDFN Packaging
SiS today announced the great success of its unprecedented
innovation of the CDFN packaging for the DRAM modules, which is different from
the traditional TSOP and BGA packaging.
The idea of the advanced CSP (Chip Scale Package) comes from the
characteristics of personalization and portability of electronic devices. The
size of packaged IC with the CSP becomes much smaller than it used to be, which
means it is almost the same size as die. The length of packaged IC will not be
longer than 1.2 times of the length of die, and the measurement of packaged IC
will not be bigger than 1.4 times of the measurement of die. SiS’s CDFN (Chip
Scale Dual Fine-pitch No-lead) packaging technology integrates the strength of
the CSP to differentiate itself from traditional packaging, which leads SiS to a
whole new world of involving in DRAM modules with a huge potential market.
The CDFN package not only reduces the ratio of measurement of IC to packaging
size, which extensively shortens the time of data transmission but also fulfills
the need of consistently increasing the I/O pin counts. Most important of all,
it has met RoHS compliance. “SiS determined to apply the CDFN packaging in
developing DDR and DDR2 modules after considering the uniqueness of this
technology. We are confident of its capabilities of high speed, low
power-consumption, low cost, and high capacity, which enables SiS to
differentiate the market.”, said Daniel Chen, CEO and President of SiS.
The CDFN package is suitable for use in IC with low I/O pin count, such as
those ICs in DRAM modules and in portable devices. It is easy to foresee the
potential profit the CDFN brings coming with the development of IA, DTV, E-Book,
WLAN/Gigabit Ethernet, ADSL, Bluetooth, and etc.