Hypertransport (HT) is a high-speed data carrying method designed to replace or supplement many of the traditional input/output methods that can cause bottlenecks on modern motherboards.

HT provides for serial point-to-point links between components at a variety of speeds and data widths, depending on the amount of bandwidth required. HT has a couple of advantages over current bus technology. Firstly, HT links can provide considerable bandwidth, and can be used on AMD64 compatible chipsets to carry data between the CPU and the main memory as well as to connect the CPU to the Northbridge (connected to the conventional AGP bus) and Southbridge (connected to the various other data buses needed in a modern computer, such as USB, PCI, ATA and S/ATA) chips on the motherboard.

Since HT links are point-to-point only, they provide a sort of highway for the data coming off the slower buses, by means of Hypertransport Bridges built into the Northbridge and Southbridge chips. Hypertransport links use packets to carry data, similar to modern Ethernet technology, where the address of the data and the data itself is all transmitted on a single wire, rather than having separate address and data lines as conventional computer data buses do.

With the speed of HT links (up to 800Mhz DDR) this allows them to carry as much or more data on far fewer data lines than are required for conventional buses, in theory simplifying motherboard design for manufacturers.

The idea then, is that point-to-point Hypertransport links are built between the CPU and the Northbridge, and between the Northbridge and the Southbridge, allowing the Hypertransport bridges in the chips to stream traffic from the various other buses onto these high bandwidth links and helping to reduce I/O bottlenecks.

Here are a couple of designs for Hypertransport-enabled chipsets from VIA and Ali respectively.