more about the chipsets on board

Right Hand Chip (bigger one)  The Texas Instruments TSB12LV23 is a PCI-to-1394 host controller compatible with the latest PCI Local Bus, PCI Bus Power Management Interface, IEEE 1394-1995, and 1394 Open Host Controller Interface Specifications. The chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s. As required by the 1394 Open Host Controller Interface (OHCI) and IEEE 1394A Specifications, internal control registers are memory mapped and non-prefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the TSB12LV23 is compliant with the PCI Bus Power Management Interface Specification, per the PC 98 requirements. TSB12LV23 supports the D0, D2, and D3 power states. The TSB12LV23 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132 Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision 2.1 system, deep FIFOs are provided to buffer 1394 data. The TSB12LV23 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance. The TSB12LV23 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal arbitration, and bus holding buffers on the PHY/Link interface, thus, making the TSB12LV23 the best-in-class 1394 OHCI solution. An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to 33 MHz.

Left Hand Chip (smaller) The TSB41LV03 provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE-1394 network. Each cable port incorporates two differential line transceivers. The transceivers include circuitry to monitor the line conditions as needed for determining connection status, for initialization and arbitration, and for packet reception and transmission. The TSB41LV03 is designed to interface with a link layer controller (LLC), such as the TSB12LV22, TSB12LV21, TSB12LV31, TSB12LV41, or TSB12LV01. The TSB41LV03 requires only an external 24.576-MHz crystal as a reference. An external clock can be provided instead of a crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216-MHz reference signal. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded strobe and data information. A 49.152-MHz clock signal, supplied to the associated LLC for synchronization of the two chips, is used for resynchronization of the received data. The power-down (PD) function, when enabled by asserting the PD terminal high, stops operation of the PLL. The TSB41LV03 supports an optional isolation barrier between itself and its LLC. When the ISO\ input terminal is tied high, the LLC interface outputs behave normally. When the ISO\ terminal is tied low, internal differentiating logic is enabled, and the outputs are driven such that they can be coupled through a capacitive or transformer galvanic isolation barrier as described in IEEE P1394a section 5.9.4. To operate with TI Bus Holder isolation the ISO\ on the PHY terminal must be tied HIGH. Data bits to be transmitted through the cable ports are received from the LLC on two, four, or eight parallel paths (depending on the requested transmission speed). They are latched internally in the TSB41LV03 in synchronization with the 49.152-MHz system clock. These bits are combined serially, encoded, and transmitted at 98.304, 196.608, or 392.216 Mbits/s (referred to as S100, S200, and S400 speed respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA cable pair(s). During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The serial data bits are split into two-, four-, or eight-bit parallel streams (depending upon the indicated receive speed), resynchronized to the local 49.152-MHz system clock and sent to the associated LLC. The received data is also transmitted (repeated) on the other active (connected) cable ports. Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of the remotely supplied twisted-pair bias voltage. The TSB41LV03 provides a 1.86-V nominal bias voltage at the TPBIAS terminal for port termination. The PHY contains three independent TPBIAS circuits. This bias voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. This bias voltage source must be stabilized by an external filter capacitor of 1 uF. The line drivers in the TSB41LV03, operating in a high-impedance current mode, are designed to work with external 112- microfarad line-termination resistor networks in order to match the 110- microfarad cable impedance. One network is provided at each end of a twisted-pair cable. Each network is composed of a pair of series-connected 56- micro resistors. The midpoint of the pair of resistors that is directly connected to the twisted-pair A terminals is connected to its corresponding TPBIAS voltage terminal. The midpoint of the pair of resistors that is directly connected to the twisted-pair B terminals is coupled to ground through a parallel R-C network with recommended values of 5 k microfarad and 220 pF. The values of the external line-termination resistors are designed to meet the standard specifications when connected in parallel with the internal receiver circuits. An external resistor connected between the R0 and R1 terminals sets the driver output current, along with other internal operating currents. This current setting resistor has a value of 6.3 k microfarad ?0.5%. This may be accomplished by placing a 6.34-k micorfarad ?0.5% resistor in parallel with a 1-M microfarad resistor. When the power supply of the TSB41LV03 is 0 V while the twisted-pair cables are connected, the TSB41LV03 transmitter and receiver circuitry presents a high-impedance signal to the cable and does not load the TPBIAS voltage at the other end of the cable. When the TSB41LV03 is used with one or more of the ports not brought out to a connector, the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each unused port, the TPB+ and TPB- terminals can be tied together and then pulled to ground, or the TPB+ and TPB- terminals can be connected to the suggested termination network. The TPA+ and TPA- and TPBIAS terminals of an unused port can be left unconnected. The TPBias terminal can be connected to a 1-uF capacitor to ground or left floating. The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For normal operation, the TESTM terminal should be connected to VDD, and the SE and SM terminals should be connected to ground. Four package terminals, used as inputs to set the default value for four configuration status bits in the self-ID packet, are hard-wired high or low as a function of the equipment design. The PC0-PC2 terminals are used to indicate the default power-class status for the node (the need for power from the cable or the ability to supply power to the cable). See Table 9 for power-class encoding. The C/LKON terminal is used as an input to indicate the that the node is a contender for bus manager. The PHY supports suspend/resume as defined in the IEEE P1394a specification. The suspend mechanism allows pairs of directly-connected ports to be placed into a low-power state while maintaining a port-to-port connection between 1394 bus segments. While in a low-power state, a port is unable to transmit or receive data-transaction packets. However, a port in a low-power state is capable of detecting connection status changes and detecting incoming TPBias. When all three ports of the TSB41LV03 are suspended, all circuits except the bandgap reference generator and bias-detection circuits are powered down, resulting in significant power savings. For additional details of suspend/resume operation refer to the P1394a specification. The use of suspend/resume is recommended for new designs. The port transmitter and receiver circuitry is disabled during power down (when the PD input terminal is asserted high), during reset (when the RESET\ input terminal is asserted low), when no active cable is connected to the port, or when controlled by the internal arbitration logic. The port twisted-pair bias-voltage circuitry is disabled during power down, during reset, or when the port is disabled as commanded by the LLC. The CNA (cable-not-active) terminal provides a high output when all twisted-pair cable ports are disconnected, and can be used along with LPS to determine when to power-down the TSB41LV03. The CNA output is not debounced. In power-down mode, the CNA detection circuitry remains enabled. The LPS (link power status) terminal works with the C/LKON terminal to manage the power usage in the node. The LPS signal from the LLC indicates to the PHY that the LLC is powered up and active. During LLC power-down mode, as indicated by the LPS input being low for more than 2.6 us, the TSB41LV03 deactivates the PHY-LLC interface to save power. The TSB41LV03 continues the necessary repeater function required for network operation during this low-power state. If the PHY receives a link-on packet from another node, the C/LKON terminal is activated to output a square-wave signal. The LLC recognizes this signal, reactivates any powered-down portions of the LLC, and notifies the PHY of its power-on status via the LPS terminal. The PHY confirms notification by deactivating the square-wave signal on the C/LKON terminal, and then enables the PHY-link interface.