Crucial PC27000 (DDR333) Memory Review

Crucial, from our own shopping experiences, offer very good service and fast delivery. I could tell you a little story about the differences between EEC SDRAM and Registered ECC SDRAM, but the only part that really applies to this review is that Crucial's RMA service was fast and painless. For an online retailer that is the best we can ever hope to say.

Previously we have looked at Crucials PC2100 DDR sticks of RAM (often able to clock well past 150 MHz, and sometimes 166 MHz), and this time around we get to play with some new PC2700 DDR!

With the recent JEDEC approval of the DDR333 (PC2700) standard Crucial is one of the first memory companies to release compliant DDR RAM. The key word here is compliant. There are many other memory manufacturers that have had "DDR333" RAM for several months now, but most of that memory is only DDR333 compatible rather then DDR333 compliant.

The Crucial DDR333 memory we are testing today is standard retail stuff. The DDR module is 256 MB in size and has SPD settings of 2.5-3-3 at DDR333 mode. This is very Crucial like in that it is conservative.

For those who want to live more on the wild side, our stick didn't have a single problem running 2-2-2 at 166 MHz FSB. As we can see, the DRAM is built by Micron Technologies (obviously) and has a -6ns rating.

I somehow doubt Crucial will ever had heat spreaders like other manufacturers have taken to doing, but it might be a goode idea considering how warm this memory reached after a few hours of testing.

DDR RAM at PCP2100 speeds doesn't get very hot, however with the DRAM running at PC2700 DDR speeds the TSOP-II packages did get nice and warm.

• 167 MHz Clock, 333 MHz data rate
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte)
• Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has two - one per byte)
• Programmable burst lengths: 2, 4, or 8
• Concurrent Auto Precharge option supported
• Auto Refresh and Self Refresh Modes
• FBGA package available
• 2.5V I/O (SSTL_2 compatible)
• tRAS lockout ( tRAP = tRCD)
• Backwards compatible with DDR200 and DDR266