Briefly, Hypertransport replaces the numerous separate data and addressing lines used in the above design with one or more Hypertransport Links for each direction. Each link will carry data in the form of a packet which contains both the data and the address it needs, while the Northbridge chip now takes on the role of organizing the data it receives from the AGP interface and the Southbridge chip into these Hypertransport packets and transmitting them across the link.

Hypertransport links can vary in both the speed they operate and the amount of bits they transfer in each packet. Some manufacturers have implemented a conventional bi-directional parallel bus instead of Hypertransport to carry data between the Northbridge and the Southbridge since the bandwidth requirements of the I/O subsystems linked to the Southbridge are minimal compared to the needs of the memory and graphics systems. More on this later. For a more in-depth examination of how Hypertransport works, please see PCstats preview of the Athlon 64 itself.

All the chipsets for the Athlon64 support 8x AGP.

The VIA K8T800

VIA's platform for the Opteron and the Athlon64 is the K8T800. It is offered in two varieties, the Server/workstation version for the Opteron Processor and the Performance PC platform for the Athlon64, both of which use the VT8237 Southbridge.

The major selling point of the K8T800 chipset is that it features a faster Hypertransport link (800Mhz DDR for an effective 1.6Ghz) between the CPU and the chipset than the offerings from the other companies.

As it uses a 16-bit (meaning 16bits of data in each Hypertransport packet) link, this enables the K8T800 to reach a maximum bandwidth of 3.2GB/s (1.6Ghz * 16 / 8) in each direction for a rather impressive maximum theoretical bandwidth of 6.4GB/s.

VIA argue that problems with signal interference have made many of their competitors resort to using lower speed implementations of Hypertransport, a problem which they have resolved with something called Hyper8 technology. So it looks like Hypertransport will hopefully eliminate many of the bottlenecks seen in current processor design, but with the memory bus moved off the Northbridge, any link that provides more than 3GBps will do.